The present invention relates to semiconductor devices having accurately dimensioned interconnection patterns. The present invention is particularly applicable to ultra large-scale integrated circuit (ULSI) devices having features in the deep sub-micron regime.
As integrated circuit geometries continue to plunge into the deep sub-micron regime, it has become increasingly difficult to satisfy the requirements for dimensional accuracy, particularly in integration technology which is considered one of the most demanding aspects of ULSI technology. Demands for ULSI semiconductor wiring require increasingly denser arrays with minimal spacings between and narrower conductive lines. Implementation becomes problematic in manufacturing semiconductor devices having a design rule of about 0.12 micron and under.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as device geometric shrink to sub-micron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a patterned conductive layer comprising at least one conductive feature, forming an opening through the interlayer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material. The excess conductive material or overburden on the surface of the interlayer dielectric is typically removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the interlayer dielectric and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Copper (Cu) and Cu alloys have received considerable attention as candidates for replacing aluminum (Al) in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-à-vis tungsten (W), making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, due to Cu diffusion through interlayer dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), Tungsten (W), tungsten nitride (WN), Tixe2x80x94TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the interlayer dielectric, but includes interfaces with other metals as well.
Cu interconnect technology, by and large, has been implemented employing damascene techniques, wherein a first dielectric layer, such as a silicon oxide layer, e.g., derived from tetraethyl orthosilicate (TEOS) or silane, or a low dielectric constant material, i.e., a material having a dielectric constant of no greater than 4 (with a dielectric constant of 1 representing a vacuum), is formed over an underlying pattern having a capping layer thereon, e.g., a Cu or Cu alloy pattern with a silicon nitride capping layer. A barrier layer and optional seedlayer are then deposited, followed by Cu deposition, as by electro-deposition or electroless deposition. As employed throughout this disclosure, the symbol Cu is intended to encompass high purity elemental copper as well as Cu-based alloys, such as Cu alloys containing minor amounts of tin, zinc, manganese, titanium, germanium, zirconium, strontium, palladium, magnesium, chromium and tantalum.
In implementing dual damascene techniques wherein the via is formed before forming the trench (via first-trench last), an etch stop layer, such as silicon nitride or silicon oxynitride, is deposited on the first dielectric layer. A second dielectric layer is then deposited on the etch stop layer. The etch stop layer is chosen for its high selectivity with respect to the overlying second dielectric layer. A photomask is then formed over the second dielectric layer, and anisotropic etching is conducted to form a via opening through the second dielectric layer, etch stop layer and first dielectric layer to the underlying conductive feature. Subsequently, the photomask for the via opening is removed and a photomask for a trench opening is formed overlying the second dielectric layer. Anisotropic etching is then conducted to form a trench, having a diameter wider than that of the via hole, stopping on the middle etch stop layer.
As miniaturization proceeds apace with an attendant shrinkage in the size of metal lines, e.g., metal lines having a width of about 0.2 micron and under, it becomes increasingly difficult to maintain the dimensional accuracy of the metal lines, particularly when implementing dual damascene techniques. Accordingly, there exists a need for interconnection methodology enabling the formation of metal features, such as metal lines, with high dimensional accuracy. There exists a particular need for dual damascene methodology enabling the formation of accurately dimensional metal lines having a width of about 0.3 micron and under, e.g., about 0.2 microns and under.
An advantage of the present invention is a semiconductor device having an interconnection pattern with high dimensional accuracy.
Another advantage of the present invention is a method of manufacturing a semiconductor device comprising an interconnection pattern with accurately dimensioned metal lines.
Additional advantages and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned by practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a silicon oxynitride etch stop layer/anti-reflective coating (ARC) on a first dielectric layer, the silicon oxynitride etch stop layer/ARC having an extinction coefficient (k) of about xe2x88x920.3 to about xe2x88x920.6; forming a second dielectric layer over the silicon oxynitride etch stop layer/ARC; and etching an opening in the second dielectric layer and into a portion of the silicon oxynitride etch stop layer/ARC stopping before reaching the first dielectric layer.
Embodiments of the present invention comprise via first-trench last damascene techniques comprising forming the first dielectric layer over an underlying metal feature with a capping layer thereon, such as silicon nitride, depositing a low silicon-silicon oxynitride etch stop layer/ARC having an extinction coefficient of about xe2x88x920.3 to about xe2x88x920.4, depositing a second dielectric layer, such as a silicon oxide, on the low silicon-silicon oxynitride etch stop layer/ARC, and forming a via hole through the second dielectric layer, low silicon-silicon oxynitride etch stop layer/ARC and first dielectric layer to the underlying metal feature. A trench is then formed in the second dielectric layer stopping on but removing about 60% to about 90% of the thickness of the low silicon-silicon oxynitride etch stop layer/ARC, thereby reducing capacitance. A metal, such as Cu, is then deposited to simultaneously fill the via opening and communicating trench. In implementing Cu integration technology, a barrier layer is typically deposited first with or without a seed layer followed by deposition of the Cu. Subsequently, CMP is implemented and a capping layer, such as silicon nitride, is deposited. Embodiments of the present invention include depositing the low silicon-silicon oxynitride etch stop layer/ARC by chemical vapor deposition at an increased N2O2 flow rate such that the deposited low silicon oxynitride etch stop layer/ARC has an oxygen content of about 10 at. % to about 15 at. % greater, and a silicon content of about 10 at. % to about 50 at. % less, than that of a conventional silicon oxynitride etch stop layer, such as a conventional silicon oxynitride etch stop layer having an extinction coefficient (k) of about xe2x88x921.1.
Another aspect of the present invention is a semiconductor device comprising an interconnection pattern, the interconnection pattern comprising: a metal line, having first and second side surfaces and a first width, in a trench, and a silicon oxynitride etch stop layer/anti-reflective coating (ARC) in the trench, the silicon oxynitride etch stop layer/ARC having an extinction coefficient (k) of about xe2x88x920.3 to about xe2x88x920.6.
Embodiments of the present invention include a semiconductor device having an interconnection pattern comprising a dual damascene structure wherein the silicon oxynitride etch stop layer/ARC in the trench extending between the side surfaces has a thickness of about 60% to about 90% of the thickness of the silicon oxynitride etch stop layer/ARC extending from the side surfaces away from the trench.
Additional advantages of the present invention will become readily apparent to those having ordinary skill in the art from the following detailed description, wherein embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and descriptions are to regarding as illustrative in nature and not as restrictive.